SWITCH-LEVEL DELAY SIMULATOR FOR CMOS CIRCUITS

Abstract

Due to rapid progress in VLSI technology it is possible to integrate several thousand functional elements within a real (j)tate area of chip.In account to verification prior to fabrication, extensive simulation based design is required because probing and repair of already fabricated VLSI system is difficult. The high accuracy is attributed to a sophisticated delay model, which includes an accurate representation of the waveform, a consistent and meaningful definition of delay, a consideration of waveform slope effects at both input and output of a gate, a consideration of the multiple charging/discharging paths in the circuit, and a consideration of the various fan-out effects and various cell-size effects. To represent the waveform accurately, the switching delay and slope are defined and calculated with consideration of internal chargW. To consider the internal charges when computing the waveform, a merged PN tree can be used to represent a CMOS gate. The characteristics of the PN tree can be used to evaluate the conducting paths. The relationship between the RC time constant and the slope of waveform is used to compute RC time constant and represent output waveform.