DEVELOPMENT OF AN ACCELERATED FAULT SIMULATOR FOR VLSI CIRCUITS

Abstract

An accelerated fault simulator has been developed for VLSI circuits, which detects a set of faults and provides the information about the fault coverage. This simulator accepts the circuit description in an ISCAS'85 format. A stuck-at fault model has been used for the fault simulation. The fault simulator is based upon restricting fault simulation to the fanout stems and combining - it with a backward traversal inside the Fanout Free Regions (FFRs) of the circuit. The fault simulation is further accelerated by using various techniques presented in this report. These techniques aim at parallel processing at various stages of calculation procedure. Simulation results demonstrate the efficiency of the developed tool as compared to the well known Parallel-Pattern Single-Fault Propagation (PPSFP) method.