Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/9528
Title: A STUDY OF VLSI INTERCONNECT DELAY MINIMIZATION USING CMOS-REPEATERS
Authors: Bisht, Rajani
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;VLSI INTERCONNECT DELAY MINIMIZATION;CMOS-REPEATERS;VLSI
Issue Date: 2000
Abstract: This work deals with VLSI interconnect delay minimization. The emphasis is on use of CMOS- repeaters for delay minimization . The study involves simulation of the repeater system , study of variation of transconductance of NMOS & PMOS devices with the variation of interconnect resistance and capacitance , development of program to design a repeater system and lay out design of a repeater system of a specific interconnect length. It is found that the delay is function of number of repeater stages and device dimensions. Transconductance of the devices can be tailored by varying load resistance and capacitance of any inverter.
URI: http://hdl.handle.net/123456789/9528
Other Identifiers: M.Tech
Research Supervisor/ Guide: Sarkar, S.
Agarwal, R. P.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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