A CMOS PHASE FREQUENCY DETECTOR FOR HIGH SPEED PLL WITH LINEAR PHASE TRANSFER CHARACTERISTICS

Abstract

A CMOS phase frequency detector is proposed for a PLL design. The proposed phase frequency detector has better phase transfer characteristics, operates at higher frequency and is simple in its structure. Based on the simulation results, the proposed phase frequency detector has linear phase transfer characteristics and is operating at a frequency of 24.73 MHz. The circuit uses two D-Flip Flop and two delay transmission gates. Besides, it adopts two reset functions RI and R2 to avoid the UP and DN to be logic-1 simultaneously. Thus, any mismatch current of the charge pump circuit will not affect the performance of PLL. The detector could greatly reduce the dead-zone phenomenon in the phase characteristic, which is important in low-jitter applications. In order to detect the smallest phase error, the new detector employs transmission gate in order to produce delay instead of two CMSO inverters. The circuits were simulated with the help of Tanner-Spice with the 0.2 p m CMOS technology. The dissertation work focuses on the improvement of the phase transfer characteristics simultaneously to operate at higher frequencies suitable for high speed applications. Totally four Phase frequency detectors (PFD's) designs have been simulated and compared. The results confirm that the final Phase Frequency Detector (PFD-4) design is a better one compared to other three designs. At each and every stage the results are compared with the previous PFD designs. 111