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dc.contributor.authorYadav, Bhuvnesh Kumar-
dc.date.accessioned2014-11-19T10:06:31Z-
dc.date.available2014-11-19T10:06:31Z-
dc.date.issued1998-
dc.identifierM.Techen_US
dc.identifier.urihttp://hdl.handle.net/123456789/9496-
dc.guideLal, Mohan-
dc.guidesarje, A. K.-
dc.description.abstractIn this thesis, shared-memory switches - under multicast bursty traffic• are studied and various schemes for managing multicast traffic are compared. Two schemes that have been used in practical realizations of these switches to replicate multicast cells are considered (1) Replication-at-receiving (RAR) or multiple Write multiple Read (MWMR) or copying Network scheme, where multiple copies of a multicast cell are stored in the buffer and served independently. (2) Replication-at-sending (RAS), where a single instance of a multicast cell is stored in the buffer, and the cell is replicated as it is transmitted to the output ports. There are two schemes for RAS : (a) Single Write Multiple Read (SWMR) scheme : an incoming multicast cell is not replicated, but rather is stored directly in the shared memory space in a separate logical queue. During its read cycle, multiple read operations are performed on multicast cell. (b) Single Write Single Read (SWSR) scheme : This scheme is similar to the SWMR scheme in write cycle but different to the SWMR scheme in Read cycle: A. multicast cell is read out only once with a single memory read operation and is then replicated at the output side of the switch with the help of additional hardware. In SWSR scheme two ATM cells can arrive to a given output port. To handle this situation there are two ways : (i) In first scheme, dedicated buffers are used at the output. This scheme is called SWSR multicast scheme with output buffer (SWSR-W-OB). (ii) In second scheme, output mask (OM) is used at the output. This scheme is called SWSR multicast scheme with output mask (SWSR-W-OM). Also a new scheme is proposed to manage separate logical multicast cell queue for each multicast VCI for SWSR-W-OM scheme by which average delay for multicast cell is reduced at high output loads. Performance of ATM switches are evaluated and compared for all the cases using simulation.en_US
dc.language.isoenen_US
dc.subjectELECTRONICS AND COMPUTER ENGINEERINGen_US
dc.subjectELECTRICAL ENGINEERINGen_US
dc.subjectELECTRONICS AND COMPUTER ENGINEERINGen_US
dc.subjectELECTRONICS AND COMPUTER ENGINEERINGen_US
dc.titleMANAGEMENT OF MULTICAST BURSTY TRAFFIC IN SHARED MEMORY ATM SWITCHESen_US
dc.typeM.Tech Dessertationen_US
dc.accession.number248010en_US
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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