Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/9493
Title: PERFORMANCE COMPARISON OF IP LOOKUP -ALGORITHMS ON IXP1200 NETWORK PROCESSOR
Authors: Kaur, Arvinder
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;ELECTRONICS AND COMPUTER ENGINEERING;ELECTRONICS AND COMPUTER ENGINEERING;ELECTRONICS AND COMPUTER ENGINEERING
Issue Date: 2004
Abstract: Recent growth of the Internet has led to an enormous growth in the routing table entries. Further on, with the upgrade to IPv6, the change in IP addresses from 32 bit to 128 bit will result in a dramatic increase in the size of the routing table entries. With growing demand for the higher bit rates and the increasing use of voice communication over the Internet, the router performance, in which the speed of a IP address lookup plays a key role, is becoming an issue of major importance in deciding the efficiency of the network. Earlier solutions for fast lookup were either completely software based on General Purpose Processor(GPP) or hardware (ASIC) based. Software based solutions offer flexibility while ASIC has high performance. The quest for achieving both high performance and flexible packet processing at wire speed has led to the creation of network processors. These are specialized processors which are designed for packet processing at wire speed. Due to their programmable nature and specialized hardware, IP look up schemes can be implemented more efficiently on these processors than on GPP. This dissertation work aims at implementing and comparing performances of fast and efficient IP lookup schemes on Intel's IXP 1200 network processor. A modification to an existing LPC trie based algorithm has also been proposed and implemented. Simulation results show that its performance is 1.5 times better than existing algorithms. Simulation is done using Intel's SDK(Software Development Kit) 2.01 developer workbench. The simulation results thus obtained after implementing lookup schemes are presented and compared. The IXPI200 architecture is. also discussed to provide directions for future optimizations.
URI: http://hdl.handle.net/123456789/9493
Other Identifiers: M.Tech
Research Supervisor/ Guide: Misra, Manoj
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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