A STUDY OF VOLTAGE SCALING EFFECTS AND HIGH SPEED TECHNIQUES IN DYCML CIRCUITS

Abstract

In present dissertation work, supply voltage scaling effects and multiple threshold voltage techniques in Dynamic Current Mode Logic (DyCML), which are useful in low power—high performance VLSI system design, are simulated for comparative study with conventional CMOS design style. Reduced output voltage swing logics, MOS Current Mode logic and Dynamic MOS Current Mode Logic (DyCML) styles are discussed. Using a first-order model of the energy and delay of MOS circuit, effects of reduction in supply voltage and threshold voltage are discussed. The Gates, NOT, NAND and XOR of conventional CMOS, DyCML, MTDyCML and MTDyCML with sleep signal (MTDyCML WSS) are implemented and simulated for comparative study purpose. Layouts of all above three Gates of each above logic style are drawn using with 2.0μm standard CMOS process technology from MOSIS. Layout drawing and Simulation are done with help of Tanner EDA Tools. Simulation results show that DyCML circuits are superior, in terms of power and delay, to conventional CMOS logic style in bigger circuits.