MINIMIZATION OF POWER DISSIPATION IN REPEATER LOADED RLC INTERCONNECTS

Abstract

Repeaters are often used to drive high impedance interconnects. A tradeoff exists, however, between the transient power dissipation and the minimum propagation delay in sizing long interconnects driven by the optimum repeater system. Optimizing the line width to achieve the minimum Power Delay Product, however, can satisfy current high speed, low-power design objectives. The Power-Delay-Area-Product (PDAP) criterion is an efficient technique to size the interconnect within a repeater system. The PDAP criterion satisfies the power dissipation, speed and area constraints. The dissertation work focuses on changing the width of a repeater loaded interconnect system for different line lengths, minimizing signal propagation delay, the optimum values for short circuit power and thus total transient power, Power delay product (PDP) and finally including area to the power delay product, Power delay area product (PDAP). At each and every design criteria, the simulated results are compared with analytical results. Analytical calculations are done using Genetic algorithms in MATLAB. Tanner tools are used for simulation purpose. The 0.251im CMOS technology is