AN ANALYTICAL STUDY OF DYNAMIC LOGIC CIRCUITS FOR VLSI. APPLICATIONS

Abstract

In this work MOS model, namely the a-power law MOS model, is used. This model takes into account the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs. As the model is simple, it is applied for handling dynamic MOSFET circuits analytically and can predict the circuit behavior in the submicrometer region quite accurately. Using this model, generalized expressions are derived for the delay and the short-circuit power dissipation encountered in Dynamic CMOS circuits. The analytical results obtained from the developed expressions are compared with TSPICE simulations (level 49) for dynamic logic circuits using 0.18μm CMOS technology and also with the already existing expressions of Dynamic logic circuits