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|DESIGN AND IMPLEMENTATION OF HIGH-SPEED CLOCKLESSRESIST SERIAL-LINK TRANSCEIVER", ERROR-
|ELECTRONICS AND COMPUTER ENGINEERING;ELECTRONICS AND COMPUTER ENGINEERING;ELECTRONICS AND COMPUTER ENGINEERING;ELECTRONICS AND COMPUTER ENGINEERING
|Serial link transceivers for inter-chip communication in asynchronous VLSI systems achieve high offchip data rates by using multiplexing transmitters and demultiplexing receivers. It interfaces parallel on-chip data paths with high-speed, serial off-chip buses. Clockless transceiver uses a token-ring architecture that eliminates complex clock generation and synchronization circuitry of synchronous transceivers. Furthermore, clockless receiver dynamically self-adjusts its sampling rate to match the bit rate of the transmitter. This dissertation work focuses on error in received bit due to signal degradation on the offchip serial interconnect.- Multiplexed transmitter and demultiplexed receiver circuits are redesigned using asynchronous design methodology for the developed error detection and correction method. Simplicity of circuit is maintained in comparison to synchronous architecture in achieving deadlock free communication, due to. error, at moderately high speed. All the communications are described using CHP (communicating hardware process) language. Circuits are designed and simulated using Tanner tools for bit rate and bit width. The 0.18iem CMOS technology is used
|Research Supervisor/ Guide:
|Agarwal, R. P.
|Appears in Collections:
|MASTERS' THESES (E & C)
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