HIGH SPEED IMPLEMENTATION OF ADVANCED ENCRYPTION STANDARD

Abstract

Symmetric-key block ciphers encrypt data and can be used to provide confidentiality for network transactions, stored data and programs. Such support for confidential information is important on all Internet-connected computers and computing devices due to the ease of eavesdropping attacks on the public Internet and wireless networks. The data rate is growing rapidly. The encryption and decryption processes are time consuming and slow, down the communication process. Thus there is a need for the speedup of the encryption process. Otherwise, the delay due to encryption will become an overhead in the current high-speed data transfer. The speed of the encryption is becoming an important factor along with the strength of the algorithm. Advanced Encryption Standard (AES) is a symmetric key encryption technique that has been issued by NIST as a new standard encryption technique to replace the Data Encryption Standard. The dissertation work is aimed at an implementation of a high speed AES. The chip architecture and the design optimizations those make high throughput possible have been presented. The code for the implementation has been written in VHDL. The functional verification of the modules written in VHDL has been done using the ModelSim 5.7 simulation package. The synthesis of the design is done using the Xilinx WebPack 6.2. The chip is implemented on Virtex 2Pro device. iii