Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/9456
Title: DESIGN AND PERFORMANCE CHARACTERISTICS OF A HIGH SPEED CMOS ADC
Authors: Maman, Neelam
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;ELECTRONICS AND COMPUTER ENGINEERING;ELECTRONICS AND COMPUTER ENGINEERING;ELECTRONICS AND COMPUTER ENGINEERING
Issue Date: 2004
Abstract: Analog to digital converters are an important system building block, as an interface between analog and digital world. With the growing market of portable electronic systems such as wireless communication devices, hearing aids, consumer electronics etc., AID converters and other interface elements that dissipate the lowest possible power and operate on the supply voltages compatible with the digital parts of the system are in great demand. The goal of this dissertation is to design and analyze an ADC that operates with sampling frequencies as high as 70-75MHz with lowest power consumption and operate on supply voltage down to 2.5V for compatible with the low power digital portion of the design as well as occupy less chip area. Flash analog to digital converters, also known as parallel ADC's are the fastest way to convert an analog signal to a digital signal. However power consumption and chip area required for the implementation of a flash converters have practical limits at higher resolution. So we have chosen a Two-step approach. This dissertation presents the design technique for an 8-bit, Two step flash ADC in 0.35μm CMOS technology. The most stringent requirement for flash ADC is a very low offset comparator. Comparator has been designed with 0.44mW(worst case) power consumption with 0.2mV offset and is working up to 150MHz sampling frequency. Then a thermometer type encoder has been implemented to extract the MSB bits using ROM logic. A high speed DAC using current mode technique is designed. The power consumption of this unit is 1.6mW. This type of DAC is useful for high speed applications as no op-amplifier is required in this technique. Finally differential amplifier as a subtractor/residue amplifier is implemented. Then all the units are connected and waveforms at the various points are obtained and analyzed. Layout of the CMOS ADC and its functional parts is then generated using Layout editor in 2μm technology. After drawing layout design rule checking is done using design rule checker. Spice file of the layout is generated by running the Spice file compiler. Layout performance is then analyzed. It has been found that design technique holds good even for 2μm technology,
URI: http://hdl.handle.net/123456789/9456
Other Identifiers: M.Tech
Research Supervisor/ Guide: Agarwal, R. P.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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