1. Shodhbhagirathi @ IITR
  2. ELECTRONICS AND COMMUNICATION ENGINEERING (FORMERLY ELECTRONICS & COMPUTER ENGINEERING)
  3. MASTERS' THESES (E & C)
Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/9436
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dc.contributor.authorAgarwal, Pushpendra Kumar-
dc.date.accessioned2014-11-19T08:54:50Z-
dc.date.available2014-11-19T08:54:50Z-
dc.date.issued1996-
dc.identifierM.Techen_US
dc.identifier.urihttp://hdl.handle.net/123456789/9436-
dc.guideHasan, Mohd.-
dc.guideSarkar, S.-
dc.description.abstractThe CMOS op-amps with two fixed topologies are analyzed and the results are presented in the form of design equations alid procedures. Trade-offs among such factors as bandwidth, gain, phase margin, bias currents, signal swing, slew rate and power dissipation are made evident. Closed form expressions are developed and a sequence of design steps is established. Using these design equations a CAD tool for automatic design of fixed topology CMOS op-amps is generated. The results of PGPICE simulations are shown to agree very well with that of CAD tool,en_US
dc.language.isoenen_US
dc.subjectELECTRONICS AND COMPUTER ENGINEERINGen_US
dc.subjectELECTRONICS AND COMPUTER ENGINEERINGen_US
dc.subjectELECTRONICS AND COMPUTER ENGINEERINGen_US
dc.subjectELECTRONICS AND COMPUTER ENGINEERINGen_US
dc.titleA CAD TOOL FOR AUTOMATIC DESIGN OF FIXED TOPOLOGY CMOS OPAMPSen_US
dc.typeM.Tech Dessertationen_US
dc.accession.number247671en_US
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