Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/9395
Authors: Chauhan, D. S.
Issue Date: 1993
Abstract: MULTISTAGE INTERCONNECTION NETWORK are used in all multiprocessing systems for communication between the processors and/or the memory modules used. A baseline network is proposed in [WU & FENG, 1980] which can serve as a reference for evaluating the relationship among most existing ;interconnection networks. Also the routing schemes developed for Baseline Network can be used by an interconnection network of isomorphic class. So we have chosen the baseline network to work with. A conventional baseline consists of 2x2 switching elements. For networks of large size, number of stages and number of switching elements required become quite large. The propagation delay also increases from input to output. Also, for large networks chances of link failure increase because of increased number of interconnection links. So, what Is desired, is a modular system design of switching elements to overcome these problems and to support VLSI implementation for large networks. Such a switching module is proposed by WU & LIN in 1985. In present work, we have proposed modifications in the conventional baseline network using the above mentioned switching modules. The proposed network while retaining the properties of conventional baseline network also provides a good deal of hardware saving , high flexibility & programmability and greatly enhanced permutational capability. A controlling algorithm has (i_i_i_) been developed and implemented for controlling the different modules in the network, according to the permutation desired. The network has been named as MODIFIED •BASELINE. NETWORK. Fault .diagnosis and fault tolerance of modified baseline network have also been considered. An algorithm for detection and diagnosis of -single 1 ink "'aült '•`'has been ' developed and implemented. Fault-tolerance capability of this network is increased by providing multiple disjoint paths between every input and output. These additional "iaths"mFe.obtained by adding an extra stage of modules. (
Other Identifiers: M.Tech
Research Supervisor/ Guide: Singh, Kuldip
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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