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DC Field | Value | Language |
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dc.contributor.author | Roy, Bipin Kumar | - |
dc.date.accessioned | 2014-11-19T08:05:35Z | - |
dc.date.available | 2014-11-19T08:05:35Z | - |
dc.date.issued | 1993 | - |
dc.identifier | M.Tech | en_US |
dc.identifier.uri | http://hdl.handle.net/123456789/9390 | - |
dc.guide | Kumar, Padam | - |
dc.description.abstract | The rapid development of Very Large Scale Integrated (VLSI) technology and the need of very reliable multiprocessor network has opened up new frontiers of research in the field of fault-tolerant multiprocessor network. A multiprocessor network is represented by a graph whose nodes are the processors and the edges are interprocessor communication links. Simulation studies of reconfiguration strategy for k-Fault-tolterent multiprocessor nonhomogeneous symmetric d-ary tree (NST) network has been done in this dissertation. A supergraph S[k,T] of a tree T is a k-FT realization of T, if S[k,T] contains a subgraph Isomorphic to T, after removal of any k nodes. It was _.carried out- in two parts. Part-I- deals with the. design and reconfiguration strategy for k<d and the Part-II deals with the design and reconfiguration strategy fof kid. | en_US |
dc.language.iso | en | en_US |
dc.subject | ELECTRONICS AND COMPUTER ENGINEERING | en_US |
dc.subject | ELECTRONICS AND COMPUTER ENGINEERING | en_US |
dc.subject | ELECTRONICS AND COMPUTER ENGINEERING | en_US |
dc.subject | ELECTRONICS AND COMPUTER ENGINEERING | en_US |
dc.title | SIMULATION STUDIES OF RECONFIGURATION STRATEGY FOR K-FT MULTIPROCESSOR NETWORK | en_US |
dc.type | M.Tech Dessertation | en_US |
dc.accession.number | 245952 | en_US |
Appears in Collections: | MASTERS' THESES (E & C) |
Files in This Item:
File | Description | Size | Format | |
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ECD245952.pdf | 2.32 MB | Adobe PDF | View/Open |
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