1. Shodhbhagirathi @ IITR
  2. ELECTRONICS AND COMMUNICATION ENGINEERING (FORMERLY ELECTRONICS & COMPUTER ENGINEERING)
  3. MASTERS' THESES (E & C)
Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/9369
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dc.contributor.authorGupta, Pankaj-
dc.date.accessioned2014-11-19T07:50:45Z-
dc.date.available2014-11-19T07:50:45Z-
dc.date.issued1993-
dc.identifierM.Techen_US
dc.identifier.urihttp://hdl.handle.net/123456789/9369-
dc.guideKumar, Padam-
dc.guideGupta, J. P.-
dc.description.abstractStarting with the observation that the speed of computation for some problems needs to be much higher than is presently achievable and that the best hope for achieving the required speed is through the use of parallel hardware, several novel parallel computer architectures with some interesting properties have been developed. A prototype data driven parallel computer built at University of Manchester,- Manchester, England, uses low way technology and yet is capable of executing about 3M instructions/sec. This dissertation attempts to realize the various modules of this prototype machine on PC. The objective has been to keep machine realization comprehensive and not make it complicated by including each and every detail of dataflow machine. The principles that go into the making of this type of machine have been highlighteden_US
dc.language.isoenen_US
dc.subjectELECTRONICS AND COMPUTER ENGINEERINGen_US
dc.subjectREALIZATION-MANCHESTER DATAFLOW MACHINEen_US
dc.subjectPCen_US
dc.subjectPARALLER HARDWAREen_US
dc.titleREALIZATION OF MANCHESTER DATAFLOW MACHINE ON PCen_US
dc.typeM.Tech Dessertationen_US
dc.accession.number245940en_US
Appears in Collections:MASTERS' THESES (E & C)

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