Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/9365
Authors: Padmanabham, Ponnada
Issue Date: 1995
Abstract: Cache coherence protocols state a set of rules to be Implemented by the cache memories, CPUs and main memory for preventing different versions of the same data item from appearing in multiple caches. This dissertation uses discrete event driven simulation to compare the performances of Adaptive cache coherence protocol and Extended write once protocol,that are proposed for the hierarchical cache structured multiprocessor systems. A hierarchical cache structure, which is a tree structure having main memory at the root and processors at the leaves, is simulated. Each node represents a cache and has four children connected to it through a shared bus. FCFS queues are used to model access conflicts of buses and cache memories. Memory references are generated based on the work load model, to take Into account the locality properties of programs. A memory request visits a subset of queues to get the desired data item. The routing behaviour of a memory request depends on the nature of the request (read or write), the place where the request block is located, and the state of the block. The performance metric used is the processing power, defined as the sum of average processor utilizations of all the processors. The effects of various parameters on system performance are studied by plotting processing power as a function of the parameter. From the results, it is observed that the Adaptive cache coherence protocol gives 15 to 30 percent performance improvement over the Extended write once protocol. The simulation program is written in C language and run under UNIX environment on TATA ELXSI POWER SERIES 3200 system.
Other Identifiers: M.Tech
Research Supervisor/ Guide: Garg, Kumkum
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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