STUDIES IN LOGIC SIMULATION - AN EVENT DRIVEN APPROACH

Abstract

The design of large digital systems, and , in particular, the design of VLSI systems have Increased the importance of logic simulation in the overall design process. Extensive simulation based design verification prior to fabrication is required because probing and repair of already fabricated VLSI systems is difficult. Traditional discrete event simulators employ sequential algorithms. As systems have grown, simulation tasks have become a significant bottleneck in the design cycle. Parallel processing seems to be only answer to address this bottleneck. Due to rapid progress in VLSI technology it is possible to integrate several thousand functional, elements within a real state area of chip at reasonable cost. the sequential algorithms is required to be modified to suit multiprocessing. This dissertation aims at analysing such an approach by considering five major factors that affect the performance: Synchronization algorithm , circuit structure, timing granularity, target architecture and partitioning.