Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/9332
Title: STUDY OF DEGRADATION EFFECT/DEEP LEVEL (EL-2) ON 3-5 GROUP COMPOUND SEMICONDUCTORS & DEVICES
Authors: Tiwari, Chandra Prakash
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;DEGRADATION EFFECT;SEMICONDUCTORS;DLTS DATA
Issue Date: 1995
Abstract: Now a days, most of modern devices are made from 3-5 group compound semiconductors. These are widely used for making LED's, Solar Cells, Photodetectors, Lasers, Microwave Devices and other Opto-Electronics devices. Due to this, properties of several 3-5 group semiconductors•\are being investigated. Deep levels in these semiconductors, be they radiative or non-radiative centres, are usually responsible for the degradation , of performance of semiconductor devices. In order to evaluate the merits of 3-5 group devices, it is necessary to detect and characterize deep levels which may present. In this dissertation work, Effect of deep levels on many devices has been studied i.e. on Bistable Optically Controlled Semiconductor Switch, Laser, Photodiode , Solar Cell, LED, FET and HEMT etc. Knowledge of nature and origin of these levels is, therefore of great interest. Particularly in this work, origin of the deep level EL-2 (E -0.83 eV)has been studied from the analysis c of DLTS data on the emission rate variation with temperature. GaAs and other ternary 'compounds grown by different techniques like, Bulk, VPE, MBE, MOCVD/ OMVPE etc. were subjected to such a study. It has been shown that the emission rates are different in different samples although their activation energies are the same, signifying that intrinsic crystal defects are mainly responsible. ' From the comparative studies on hole traps in anneled.VPE GaAs samples, it has been concluded that Ga vacany complex is responsible for 0.83 eV electron trap level and As vacany complex for the 0.64 eV hole trap level. It has also been resolved that 0.83 and 0.76 eV levels are two different levels in GaAs. Metal contacts on silicon have also been fabricated and their behaviour with annealing temperature has been studied. The lowest contact resistance is obtained at some specific annealing temperature and increases if this temperature is changed in either direction from the minimum.-
URI: http://hdl.handle.net/123456789/9332
Other Identifiers: M.Tech
Research Supervisor/ Guide: Saxena, A. K.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' THESES (E & C)

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