Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/9300
Title: SIMULATION STUDIES FOR MAPPING PROCESS GRAPHS ON A MULTIPROCESSOR NETWORK
Authors: Saxena, Akhil
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;SIMULATION STUDIES-MAPPING PROCESS;GRAPHS-MULTIPROCESSOR NETWORK;BINARY DE BRUIJN MULTIPROCESSOR
Issue Date: 1993
Abstract: Parallel processing is characterized by division of a process into several Independent subprocesses and concurrent execution of the mutually Independent subprocesses. Functional languages offers an elegant solution to the exploitation of parallelism. The main advantages are that the programmer does not have to design •static modules for each processor of multinet also, it in itself guarantee mutual exclusion and synchronization to establish communication protocols between tasks. This allows the programmer to concentrate on creative activities of designing parallel algorithms rather than worrying for communication and synchronization between processors The inclusion of parallelism has led to the problem of Interprocessor communication which did not exist in uniprocessor system. In the multiprocessor environment, various subprocesses are assigned to different processors, consequently the processor need to communicate the result of their computation.The interprocessor communication and synchronization undermine the advantage gained by concurrent execution. Mapping is concerned with assigning program modules or subprocesses among processors of the multinetwork subject to minimizing the total number of routing steps and distributing load evenly among processors. This dissertation reports the work on evaluating the performance of mapping process graphs on a multiprocessor network through simulation.The work aims for designing an optimum mapping strategy to minimize communication overheads and load imbalance among processors. (i) For simulating the multiprocessing environment the behaviour of functional program is abstracted by generating arbitrary process.graphs.Binary De Bruijn Multiprocessor (BDM) network of variable size are simulated.Three mapping algorithms which maps the arbitrary process graph on BDM network of different sizes are designed, implemented and compared for their performance.
URI: http://hdl.handle.net/123456789/9300
Other Identifiers: M.Tech
Research Supervisor/ Guide: Kumar, Padam
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' THESES (E & C)

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