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dc.contributor.authorKhan, Parvez Mahmood-
dc.date.accessioned2014-11-19T05:43:29Z-
dc.date.available2014-11-19T05:43:29Z-
dc.date.issued1992-
dc.identifierM.Techen_US
dc.identifier.urihttp://hdl.handle.net/123456789/9265-
dc.guideAnurag-
dc.description.abstractWith rapid advancements in IC technology, digital circuits are becoming more dense and more complex. Consequently, the conventional testing methods are grossly unable to cope with the requirements of increased circuit size and complexity and hence, are infeasible. One promising approach for reducing testing difficulties is to consider digital circuit's testability as early as possible in the design cycle. Several techniques are available for testability analysis of digital circuits. In each of these techniques, the testability of a. digital circuit is directly related to the difficulty of controlling and observing the logical values of internal nodes from primary inputs and primary outputs respectively. If the testability analysis is faster and it accurately predicts the difficulty of testing, then areas of circuit which pose potential difficulties in testing can be identified early in the design cycle, and corrective actions can be taken as a part of the designen_US
dc.language.isoenen_US
dc.subjectELECTRONICS AND COMPUTER ENGINEERINGen_US
dc.subjectDIGITAL CIRCUITSen_US
dc.subjectCAMELOTen_US
dc.subjectSCOAPen_US
dc.titleTESTABILITY ANALYSIS OF DIGITAL CIRCUITS BASED ON CAMELOT AND SCOAPen_US
dc.typeM.Tech Dessertationen_US
dc.accession.number245602en_US
Appears in Collections:MASTERS' THESES (E & C)

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