A SYNTHESIS AND VALIDATION TOOL FOR COMPUTER COMMUNICATION PROTOCOLS

Abstract

Communication plays an important role in computer networks and distributed systems. The increasing complexity and veriety of protocols have required the adoption of powerful methods and tools to facilitate their design. To avoid errors and ambiguities, numerous formal models and verification techniques have been proposed and applied to the verification and construction of communication protocols. In this dissertation work, the synthesis and validation tool for computer communication protocol was developed. The Finite State Machine model has been used for specification of protocols. The validation technique implemented is Reachability analysis to 'detect logical errors, like unspecified reception, state dead locks, and buffer overflows. And an automated synthesizing technique has been implemented for the synthesis of error free protocol for a given incomplete Finite State Machine. The system has a graphical interface to facilitate the application of these techniques. The source code for the system is written in C-programming language and compiler used is turbo C.