Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/9211
Title: FUNCTIONAL TESTING OF THE 8085 MICROPROCESSOR
Authors: s., Manjunatha Prasanna
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;FUNCTIONAL TESTING;8085 MICROPROCESSOR;GRAPH-THEORETIC MODEL
Issue Date: 1990
Abstract: Functional testing of microprocessors uses the instruction repertoire and the architecture of the microprocessor as the parameters of test generation. S.M.Thatte and J.A.Abraham have jointly proposed a method of functional testing of microprocessors in the 9th annual international conference on FTC. They have developed a general graph-theoretic model (S-graph) for microprocessors at the register level and have presented the functional level fault models. Based on their approach an attempt has been made here in generating the test patterns for the popular INTEL 8085 microprocessor. Two different S-graphs (Si and-S2) have been derived for 8085. Si has been referenced in generating test patterns for detecting register decoding faults and S2 has been used for detecting data storage/transfer faults. These test patterns are valid instructions of the 8085, unlike the test patterns of the classical methods which are arbitrary bit vectors. In order to check for the validity of these test patterns the 8085 processor was simulated at the T-state level. Different types of faults were introduced into the simulated model in the register decoding and data storage/ transfer functions. The test patterns derived were found successful in detecting the
URI: http://hdl.handle.net/123456789/9211
Other Identifiers: M.Tech
Research Supervisor/ Guide: Sarje, A. K.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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