DESIGN METHODOLOGY FOR A SELF CHECKING MICROPROCESSOR

Abstract

The traditional design of electronic circuits is based on the fault-intolerant approach. Correct operation is hence not guaranteed in the presence of any operational fault. Self-checking logic, on the other hand, is aimed at the online detection of faults. Thus, by incorporating self-checking logic into the design, reliable operation can be achieved. In this dissertation, .a self-checking microprocessor architecture is proposed. This has been modelled around Iitel' s representative 8-bit microprocessor, the 8085A. Self-checking strategies for the different functional units of the microprocessor are reviewed and selectively applied to the design of the register section, the arithmetic and logic unit and the control unit. The register section consists of the register file and, additionally, check logic for the decoders. Single bit parity is used over the data transfer paths. The ALU is implemented using an interconnection of totally self-checking PLAs. A self--checking microprogrammed control unit is developed with additional check bits to validate sequencing operation. Microinstructions have been -coded for normal instruction execution in the foreground mode and to carry out diagnostics activity simultaneously, in the background mode.