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DC Field | Value | Language |
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dc.contributor.author | S, Suresh Banu | - |
dc.date.accessioned | 2014-11-18T10:03:44Z | - |
dc.date.available | 2014-11-18T10:03:44Z | - |
dc.date.issued | 1988 | - |
dc.identifier | M.Tech | en_US |
dc.identifier.uri | http://hdl.handle.net/123456789/9155 | - |
dc.guide | Joshi, R. C. | - |
dc.description.abstract | Artificial Intelligence processing has become the corner stone of many application areas such as expert system, computer- vision, speech recogonition, robotics and natural language processing, etc. As the techniques of Al processing becomming.well known, the requirement for higher performance system architecture is in demand. The earliest computer design to support Al processing was the implementation of functional languages on conventional machines. Because of the sequential nature of execution of these machines, the inherent parallelism in Al algorithms cannot be exploited. With the introduction of VLSI technology, we observed a shift of functions from software to hardware. Thus it offered much flexibility to adopt to Al applications. The large degree of nondeterminism in Al algorithms provides an additional source of parallelism. Hence, for efficient. Al "processing a parallel architecture is most suited. In this dissertation various architectural design issues for Al machines are examined. Based upon . these considerations, a parallel architecture, -based on data flow model is suggested. The suitability of using Prolog as the Kernel language for the proposed architecture is also examined. Since each processing element is having a local memory for storing the program and almost all software functions are implemented in hardware by taking advantage of VLSI technology, the proposed Al machine architecture can provide better Al processing capability. | en_US |
dc.language.iso | en | en_US |
dc.subject | ELECTRONICS AND COMPUTER ENGINEERING | en_US |
dc.subject | ELECTRONICS AND COMPUTER ENGINEERING | en_US |
dc.subject | ELECTRONICS AND COMPUTER ENGINEERING | en_US |
dc.subject | ELECTRONICS AND COMPUTER ENGINEERING | en_US |
dc.title | A PARALLEL ARCHITECTURE FOR At APPLICATIONS | en_US |
dc.type | M.Tech Dessertation | en_US |
dc.accession.number | 179648 | en_US |
Appears in Collections: | MASTERS' THESES (E & C) |
Files in This Item:
File | Description | Size | Format | |
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ECD179648.pdf | 2.89 MB | Adobe PDF | View/Open |
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