Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/9126
Title: IMPLEMENTATION OF FAULT SIMULATION TECHNIQUES
Authors: Aggarwal, Rahul
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;ELECTRONICS AND COMPUTER ENGINEERING;ELECTRONICS AND COMPUTER ENGINEERING;ELECTRONICS AND COMPUTER ENGINEERING
Issue Date: 1987
Abstract: Advances in digital technology has led to an increase of circuit complexity and its size in terms of the number of gates used. So it has become essential to use computer aided design and testing of digital circuits. One of the basic tools for this is fault simulation,. Various fault simulation techniques and their alter-natives have been proposed in literature. In this work Parallel Simulation, Deductive Simulation, (Priti.calpath tracing and statistical fault analysis have been implemented on DW 2050. The implementations are valid for combinational circuits. The single-stuck'-at fault model has been used. The results have been presented in terms of the C.F.U. requirements of the different techniques. The results indicate that parallel simulation requires minimum C.P.U. time.
URI: http://hdl.handle.net/123456789/9126
Other Identifiers: M.Tech
Research Supervisor/ Guide: Singh, Kuldip
Nanda, N. K.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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