Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/9121
Title: DIGITAL PHASE LOCKED LOOPS FOR FREQUENCY SYNTHESIS IN T.V.
Authors: Agarwal, Nidhi
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;ELECTRONICS AND COMPUTER ENGINEERING;ELECTRONICS AND COMPUTER ENGINEERING;ELECTRONICS AND COMPUTER ENGINEERING
Issue Date: 1987
Abstract: With the tremendous advances in the digital technology, an increasing use of digital techniques in a T V receiver have been made. Digital television set processes television signals after they have been demodulated. Demodulated signals from the IP amplifier an fed to the audio and video codec units, which convert the analog signal into digital and pass them along to audio and video processor units. With long term experience in the field of tuning s,'n,d control for television receivers and video tape recorder, a rapid increase of frequency counters and DPLL synthesizer have been seen • A f re quency synthesizer is a device that generates a large number of precise frequencies from a single reference frequency. A microcomputer controlled frequency sync, zexsis a unique electronic tuning system in television. This dissertation deals with various digital techniques in a television receiver with special emphasis on frequency synthesis by a PLL in a T V receiver. A hardware impiementatj of a Digital phase locked loop is also done with TTL inte drat, ckts. This DPLL has been tested at a frequency of 1.5 KCiz.
URI: http://hdl.handle.net/123456789/9121
Other Identifiers: M.Tech
Research Supervisor/ Guide: Mehra, D. K.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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