Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/9104
Title: A STUDY ON TESTABILITY AND FOLDABILITY ASPECTS OF A PLA
Authors: Garg, Amit
Keywords: ELECTRONICS AND COMPUTER ENGINEERING
ELECTRONICS AND COMPUTER ENGINEERING
ELECTRONICS AND COMPUTER ENGINEERING
ELECTRONICS AND COMPUTER ENGINEERING
Issue Date: 1987
Abstract: Programmable logic arrays (pLs) are fast catching up the imginatin of VLSt designers due to th!r flexible but hig.y regular structure. This focuses particular at'tentior on their testing and cOst.eectLve chip imple entat1on. Both of these aspects re considered in the present dissertation work. Two new algorithms are proposed for this a review of the various PLA concepts and some existing repz'e sentattve PtA testing and folding sohemewo The proposed PtA testing scheme comers almost all the possible faults in a PtA and the new folding aigoritbm produces more compact pact PLAs than other existing aorit1ins.
URI: http://hdl.handle.net/123456789/9104
Other Identifiers: M.Tech
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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