DESIGN OF A UNIVERSAL LOGIC BLOCK FOR VLSI BUILT-IN TESTING

Abstract

System designers in the VLSI environment have been challenged by the increasing complexity and density of the circuits because leaps in integrated circuit technology areJoccuring at a faster rate than advancements in test technology. In recent years, built—in tests have made sub-stantial inroads into territories which were once undisputed domain of functional testers, particularly in VLSI circuits. Based on Level Sensitive Scan Design, several built—in test techniques have been successfully implemented by the VLSI manufacturers. J ` The high densities and microscopic size of VLSI chips render conventional testing `methods .insufferably expensive and impractical. But the very same high densities render feasible,the inclusion of testing and measurement circuitry on the chip itself, thus giving rise to the approach of self—testing. But this also demands that (i) only a modest amount of circuitry is added to the chip for the purpose of testing and (ii) this additional circuitry does not unduly degrade the performance of the original circuitry. Currently used approaches, inspite of being practical, have their own pitfalls in one way or the other. An approach to overcome these deficiencies for built—in testing of VLSI circuits has been discussed in this dissertation.