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DC Field | Value | Language |
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dc.contributor.author | Kumar, Ashok | - |
dc.date.accessioned | 2014-11-18T08:06:45Z | - |
dc.date.available | 2014-11-18T08:06:45Z | - |
dc.date.issued | 1986 | - |
dc.identifier | M.Tech | en_US |
dc.identifier.uri | http://hdl.handle.net/123456789/9036 | - |
dc.description.abstract | The PLA implementation of logic functions circuits offers many advantages. The advantages offered by PLA. are following: l: Irregular logic functions can be rapped into regular structures8. 2. Functions may be significantly changed without requiring major changes of either the design or layout of the PLA6. 3. A great logical complexity is possible' using PLA, since. a plane may contain 19000 to 20,000 nodes 6, 4. PLA approach is very easy to automate with computer aided design techniques. A designer can implement logic functions easily and check the design for errors• 1.6 THE PLA IMPLEIC-, WED: The package has been developed to implement comb inat is;nal circuits using PLA in AND-OR form. That is, the output is in the sum-of-products term form. The technology used for designing is n-MOS self aligned poly silicon ;ate technology. To make the inputs and outputs compatible with TTL logic, a voltage 5V, is taken as VDD. The default value of 'the parameters Lambda, Oxide thickness, output capacitive load and mobility are 5 microns, 800 A°, 0.5 pF/output, and 600 cm,2/V sec respectively. | en_US |
dc.language.iso | en | en_US |
dc.subject | ELECTRONICS AND COMPUTER ENGINEERING | en_US |
dc.subject | ELECTRONICS AND COMPUTER ENGINEERING | en_US |
dc.subject | ELECTRONICS AND COMPUTER ENGINEERING | en_US |
dc.subject | ELECTRONICS AND COMPUTER ENGINEERING | en_US |
dc.title | COMPUTER AIDED PROGRAMMABLE LOGIC ARRAY LAYOUT GENERATION | en_US |
dc.type | M.Tech Dessertation | en_US |
dc.accession.number | 178806 | en_US |
Appears in Collections: | MASTERS' THESES (E & C) |
Files in This Item:
File | Description | Size | Format | |
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ECD178806.pdf | 2.8 MB | Adobe PDF | View/Open |
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