Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/9036
Title: COMPUTER AIDED PROGRAMMABLE LOGIC ARRAY LAYOUT GENERATION
Authors: Kumar, Ashok
Keywords: ELECTRONICS AND COMPUTER ENGINEERING
ELECTRONICS AND COMPUTER ENGINEERING
ELECTRONICS AND COMPUTER ENGINEERING
ELECTRONICS AND COMPUTER ENGINEERING
Issue Date: 1986
Abstract: The PLA implementation of logic functions circuits offers many advantages. The advantages offered by PLA. are following: l: Irregular logic functions can be rapped into regular structures8. 2. Functions may be significantly changed without requiring major changes of either the design or layout of the PLA6. 3. A great logical complexity is possible' using PLA, since. a plane may contain 19000 to 20,000 nodes 6, 4. PLA approach is very easy to automate with computer aided design techniques. A designer can implement logic functions easily and check the design for errors• 1.6 THE PLA IMPLEIC-, WED: The package has been developed to implement comb inat is;nal circuits using PLA in AND-OR form. That is, the output is in the sum-of-products term form. The technology used for designing is n-MOS self aligned poly silicon ;ate technology. To make the inputs and outputs compatible with TTL logic, a voltage 5V, is taken as VDD. The default value of 'the parameters Lambda, Oxide thickness, output capacitive load and mobility are 5 microns, 800 A°, 0.5 pF/output, and 600 cm,2/V sec respectively.
URI: http://hdl.handle.net/123456789/9036
Other Identifiers: M.Tech
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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