1. Shodhbhagirathi @ IITR

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Issue DateTitleAuthor(s)Research Supervisor/ Guide Type
20133®DIMENSIONAL SIMULATION OF SINGLE EVENT UPSET OF 6T-SOI BASED 24 nm —FINFET -SRAM CELLJayaram, NamaniDasgupta, Sudeb; Bulusu, AnandM.Tech Dessertation
2012MECHANICAL STRESS AWARE GATE TIMING MODEL FOR COMBINATIONAL LOGIC CELLSVundavalli, SandeepBulusu, Anand; Dasgupta, SudebM.Tech Dessertation
2012MODELING AND SIMULATION OF CNT BASED GAS SENSORBasak, AnirbanDasgupta, Sudeb; Manhas, S. K.M.Tech Dessertation
2012MEMORY TESTING SCHEME FOR FinFET BASED SRAM CELLPrasad, K. DurgaDasgupta, Sudeb; Kaushik, B. K.M.Tech Dessertation
2013T.CAD EVALUATION OF FIN ARCHITECTURE ON SOI SUBSTRATE AND ITS COMPARISON WITH PLANAR FDSOI 'MOSFET AT 28nm TECHNOLOGY NODESahu, Prahlad KumarSithanandam, R.; Bulusu, Anand; Dasgupta, SudebM.Tech Dessertation
2011ULTRA-LOW POWER FLIP-FLOPS USING CLOCK GATING AND SINGLE PHASE QUASI-STATIC ENERGY RECOVERY LOGICKumbhare, Rohan VijaySaxena, Ashok K.; Dasgupta, SudebM.Tech Dessertation
2010ROBUST ANALOG VLSI CIRCUIT DESIGNKumar, AtulBulusu, Anand; Dasgupta, SudebM.Tech Dessertation
Sep-2015MODELING AND SIMULATION OF DOUBLE GATE TUNNEL FIELD EFFECT TRANSISTOR (DG-TFET)MenkaDasgupta, Sudeb; Bulusu, AnandThesis

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