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ELECTRONICS AND COMMUNICATION ENGINEERING (FORMERLY ELECTRONICS & COMPUTER ENGINEERING)
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Issue Date
Title
Author(s)
Research Supervisor/ Guide
Type
1999
. VLSI-CHIP FLOORPLAN AREA OPTIMIZATION BY GENETIC ALGORITHM
Gupta, Ravi Kant
Sarkar, S.
M.Tech Dessertation
1998
TEMPERATURE SENSITIVITY OF SHANNON IMPLANTED SILICON MESFET THRESHOLD VOLTAGE
rao, D. L. Narasimha
Sarkar, S.
M.Tech Dessertation
2002
LAY-OUT DESIGN OF ENCODER AND DECODER CHIP FOR MOBILE APPLICATIONS
Kumar, Satyendra
Joshi, R. C.; Sarkar, S.
M.Tech Dessertation
1997
PERFORMANCE STUDY OF SERIES CONNECTED GUNN DIODES FOR MICROWAVE POWER GENERATION
Sharma, Lieutenant Sanjay
Agarwal, R. P.; Sarkar, S.
M.Tech Dessertation
1998
AN ANALYTICAL STUDY OF SCHOTTKY BARRIER HEIGHT TAILORING
Ghosh, Jyotirmoy
Sarkar, S.
M.Tech Dessertation
1997
COMPUTER SIMULATION OF GUNN DIODE
Reen, Pinku
Sarkar, S.
M.Tech Dessertation
2003
STUDY OF DYNAMIC CURRENT MODE LOGIC VLSI CIRCUITS"
Singh, Rajeer
Sarkar, S.
M.Tech Dessertation
2003
CHIP LEVEL DESIGN OF 4-BIT UNIVERS. SHIFT REGISTER
Venugopal, N.
Sarkar, S.
M.Tech Dessertation
1996
A STUDY OF IMPURITY DISTRIBUTION DEPENDENCE OF MESFET GATE-DRAIN BREAKDOWN VOLTAGE
Garg, Jitendra
Sarkar, S.
M.Tech Dessertation
1996
EFFECT OF DEVICE SCALING ON MESFET GATE BIAS VOLTAGE FOR DRAIN CURRENT ZERO TEMPERATURE COEFFICIENT
Salgiya, Sudhanshu
Sarkar, S.
M.Tech Dessertation
Discover
Author
1
Agarwal, Pushpendra Kumar
1
Agarwal, Rakesh Mohan
1
Bhardwaj, Anil
1
Bhattacharya, Sumita
1
Bind, Shyam Dhar
1
Bisht, Rajani
1
Chandel, Rajeevan ( Nee Pathania)
1
Dutta, Arindam
1
Garg, Jitendra
1
Ghosh, Jyotirmoy
.
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Subject
1
CHANNEL MOBILITY
1
CHANNEL-SUBSTRATE JUNCTION
1
CHIP LEVEL DESIGN
1
CMOS BUFFERS
1
CMOS DRIVEN
1
CMOS INVERTER
1
CMOS TECHNOLOGY
1
CMOS-REPEATERS
1
CMOS-SUBTHRESHOLD OPERATION
1
COMPUTER SIMULATION
.
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Date issued
18
2000 - 2007
17
1990 - 1999
4
1980 - 1989
1
1979 - 1979
Research Supervisor/ Guide
9
Agarwal, R. P.
2
Joshi, R. C.
1
Agarwal, Rajendra P.
1
Handa, S. C.
1
Hasan, Mohd.
1
Padma, D.
1
Sinha, S. N.
Has File(s)
40
true