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Issue DateTitleAuthor(s)Research Supervisor/ Guide Type
2012CROSSTALK AVOIDANCE IN RLC MODELED INTERCONNECTS USING LOW POWER ENCODERBabu, Gunti NagendraKaushik, B. K.; Bulusu, AnandM.Tech Dessertation
2012PERFORMANCE ANALYSIS OF CARBON NANOTUBE BASED INTERCONNECTpandya, Nisarg D.Kaushik, B. K.; Manhas, S. K.M.Tech Dessertation
2011ENCODING IN VLSI INTERCONNECTSAgarwal, DeepikaKaushik, B. K.; Manhas, S. K.M.Tech Dessertation
2012MEMORY TESTING SCHEME FOR FinFET BASED SRAM CELLPrasad, K. DurgaDasgupta, Sudeb; Kaushik, B. K.M.Tech Dessertation
Nov-2015DUAL-k SPACER ENGINEERED DEVICES FOR HIGH PERFORMANCE DIGITAL CIRCUIT/SRAM APPLICATIONSPal, Pankaj KumarKaushik, B. K.; Dasgupta, SThesis
Nov-2015MODELING OF CROSSTALK EFFECTS IN CMOS GATE DRIVEN ON-CHIP INTERCONNECTS USING FDTD TECHNIQUEVobulapuram, Ramesh KumarKaushik, B. K.; Patnaik, AThesis