1. Shodhbhagirathi @ IITR

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Results 1-10 of 14 (Search time: 0.012 seconds).
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Issue DateTitleAuthor(s)Research Supervisor/ Guide Type
2012CROSSTALK AVOIDANCE IN RLC MODELED INTERCONNECTS USING LOW POWER ENCODERBabu, Gunti NagendraKaushik, B. K.; Bulusu, AnandM.Tech Dessertation
20133®DIMENSIONAL SIMULATION OF SINGLE EVENT UPSET OF 6T-SOI BASED 24 nm —FINFET -SRAM CELLJayaram, NamaniDasgupta, Sudeb; Bulusu, AnandM.Tech Dessertation
2011A TIMING MODEL OF SEQUENTIAL CIRCUITS FOR EFFICIENT STANDARD CELL LIBRARY CHARACTERIZATIONSharma, YogenderaBulusu, Anand; Saxena, Ashok KumarM.Tech Dessertation
2012MECHANICAL STRESS AWARE GATE TIMING MODEL FOR COMBINATIONAL LOGIC CELLSVundavalli, SandeepBulusu, Anand; Dasgupta, SudebM.Tech Dessertation
2013T.CAD EVALUATION OF FIN ARCHITECTURE ON SOI SUBSTRATE AND ITS COMPARISON WITH PLANAR FDSOI 'MOSFET AT 28nm TECHNOLOGY NODESahu, Prahlad KumarSithanandam, R.; Bulusu, Anand; Dasgupta, SudebM.Tech Dessertation
2010EFFFICIENT NANOSCALE VLSI STANDARD CELL LIBRARY CHARACTERIZATION USING A NOVEL DELAY MODELMikyal, SandeepBulusu, AnandM.Tech Dessertation
2010OPTIMAL DESIGN OF NANOSCALE STANDARD CELLS CONSIDERING PARASITICSPipersaniya, AnkitBulusu, AnandM.Tech Dessertation
2010ROBUST ANALOG VLSI CIRCUIT DESIGNKumar, AtulBulusu, Anand; Dasgupta, SudebM.Tech Dessertation
2011ANALYSIS OF UNDERLAP FINFET PARASITIC CAPACITANCE FOR CIRCUIT DESIGNINGRaycha, SwatiBulusu, Anand; Saxena, A. K.M.Tech Dessertation
Jun-2019DESIGN AND ANALYSIS OF NEAR THRESHOLD CMOS STORAGE ELEMENTS CONSIDERING VARIATIONS AND SOFT ERRORSKumar, Chaudhry IndraBulusu, AnandThesis

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