ON TIMED PETRINET MODELLING AND ANALYSIS OF A MULTI-MICROPROCESSOR SYSTEM

Abstract

The thesis deals with Timed Petrinet based modelling and performance analysis of Cmc - A Multi-microprocessor System. Response Time has been chosen as the measure of performance. The need for modelling and performance analysis is described first and then the suitability of a class of Timed Petrinets for this purpose is demonstrated. Timed Petrinet theory is presented in brief. Relevant details of the structure of Cm-* are given and the various memory referencing mechanisms therein are discussed. Timed Petrinet models for the three levels of memory references (Processor - local, Cluster - local and Inter-cluster) are developed and then they are analyzed using a recently developed technique.On the basis of performance analysis it is shown that the technique can even be used for validating/ modifying the design of any system. Since it is now possible to automate Petrinet analysis, this technique can be viewed as a basic tool in the Computer Aided Design of Large Scale Systems.