DESIGN AND IMPLEMENTATION OF A FAULT-TOLERANT ARITHMETIC AND LOGIC PROCESSOR

Abstract

Fault-tolerant systems are playing a vital role in a variety of fields. In many applications, repair of system is difficult or out of reach and hence failure must be eliminated or the probability if failure over specified length of time must be reduced, It is difficult to have components which are sufficiently reliable to accomplish this objective. Techniques have been developed to design a fault-tolerant arithmetic and logic processor which compute correctly in the presence of a fault. To obtain fast error-free computation the arithmetic and logic unit is duplicated and a comparator circuit compares the outputs of the ALUs continuously, and generates an error signal on occurrence of an error. The normal operation is halted temporarily, at which instant a control unit called the controller/tester receives an error signal from the comparator; and runs diagnostic routines in order to identify the faulty unit. The failty ALU is then isolated and result from the other AT,U is assumed as being the correct one for subsequent use. Redundancy techniques particularly hot standby has been used to achieve the objective ad a microprocessor ie used as e. controller/tester for identifying the faulty module. K-out-of-2K checkers have been employed to make the set-up secure against the checker being faulty. The integrated set-up has been tested for its fault-tolcre,nce.