Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/8073
Full metadata record
DC FieldValueLanguage
dc.contributor.authorPathani, Sunil-
dc.date.accessioned2014-11-11T11:22:56Z-
dc.date.available2014-11-11T11:22:56Z-
dc.date.issued2011-
dc.identifierM.Techen_US
dc.identifier.urihttp://hdl.handle.net/123456789/8073-
dc.guideTyagi, Barjeev-
dc.description.abstractIn recent times Field programmable gate array (FPGA) has been gaining popularity in implementation of digital design as they offer flexibility of being reprogrammed any number of times. The digital design for a system on chip architecture (SoC) applications is provided by FPGA. The SoC controllers so developed are much compact as compared to PLC controllers used in industrial application. In this dissertation report a digital PID controller has been designed and implemented on FPGA for level process control system. The plant taken for experimental studies carried out in this dissertation are first order (single tank) and second order (twin tank) systems. The digital controller has been implemented on FPGA kit named Spartan 3 DSP for digital implementation. The digital controller has been design using system generator approach. This report discuss in detail the procedure to use Xilinx system generator tool box approach and Xilinx ISE platform to obtain VHDL codes that can be implemented on to the FPGA platform. For the designing the PID controller, Position Algorithm has been used. The analog PID equation has been discretized using impulse invariant method. Parameter of digital PID controller are tuned using genetic algorithm.GA tool box of MATLAB R2009a is used for this purpose. The result of digital PID controller has been compared with the result obtained with analog PID controlleren_US
dc.language.isoenen_US
dc.subjectELECTRICAL ENGINEERINGen_US
dc.subjectDIGITAL PID CONTROLLERen_US
dc.subjectFPGAen_US
dc.subjectREAL TIME LEVEL CONTROL PROCESSen_US
dc.titleDESIGN AND IMPLEMENTATION OF DIGITAL PID CONTROLLER ON FPGA FOR REAL TIME LEVEL CONTROL PROCESSen_US
dc.typeM.Tech Dessertationen_US
dc.accession.numberG21128en_US
Appears in Collections:MASTERS' THESES (Electrical Engg)

Files in This Item:
File Description SizeFormat 
EED G21129.pdf6.38 MBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.