PERFORMANCE EVALUATION OF MULTILEVEL PWM' INVERTER.

Abstract

he classic configuration of PWM inverters widely developed in the last twenty years. is able to generate mostly * two level output waveforms. Many improvements have been proposed to classic configuration as regards the circuit structure, the control schemes and the generation algorithm, but the inverter performances were limited by the available number of levels to build the output voltage. To overcome these limits, several structures of multilevel inverter topologies have been recently designed and they are now capturing the attention of many power electronics industries, particularly for high power converters, but they exhibit many important advantages, in respect to the conventional two level inverters, in any applications. ■ The level of voltage and power supplied by the inverter is considerably increased, ■ Switching losses are reduced because each device switches a lower voltage. ■ The harmonic distortion of the output voltage is strongly reduced without increasing the switching frequency_. There are many problems associated with multilevel inverters. Out of which capacitor voltage unbalancing is the prominent one. The digital implementation of such a structure of multilevel inverter needs the use of a fast microprocessor or DSP, and an accurate research of suitable equations and conditions_for the calculation of different commutation angles. In this dissertation a fast personal computer based implementation using the sub harmonic generation.- algorithm performing the online calculation of the correct switching angles for the 5-level- diode clamped inverter has been presented and Capacitor voltage balancing circuit for 5-level inverter has been also presented.