PLC DESIGN IMPLEMENTATION USING FPGA ARCHITECTURE

Abstract

This work deals with the Design Implementation of a, Programmable Logic Controller(PLC). chip using VHDL programming at XILINX'S Foundation series platform supported by Modeltech's ModelSim simulator. The chip has to be designed to make a feel of a simple PLC available on FPGA. The design includes structural model development, simulation and logic synthesis using Xilinx Foundation series tool suite supported by Modelsim simulator and test environment generation. Programmable Logic Controller (PLC) is a digitally operating electronic system designed for use in an industrial environment, which uses a programmable memory for the internal storage of instructions for implementing specific functions such as logic, sequencing, timing, counting and arithmetic to control through analog or digital input / output modules, various types of machines or processes. Field Programmable Gate Array is a programmable logic array in which internal connections of logic blocks can be programmed in the field to realize the desired digital circuit. FPGA provides system designer a great deal of flexibility and many are excellent alternative to standard SSI, MSI logic devices. FPGA are a recent development of programmable logic with much higher logic and register capacity than Programmable Array Logic and Configurable Programmable Logic Devices (CPLD). FPGA are two Dimensional array of cells which implement a logic using configurable blocks and configurable routing between logic blocks. The VHDL code of the PLC is prepared based on the structural —behavioral description of the model. PLC ladder logic blocks are implemented using VHDL coding. The ladder logic blocks to be implemented are normally open contact (load input LD), normally closed contact (load inverse of input LDI), output (out), AND, OR, AND BLOCK, OR BLOCK, TIMER, COUNTER, SET, RESET and so on which are the instructions which are available in the PLC generally. VHDL System Simulator (Modelsim) is then used for simulation of the debugged VHDL code to check for the functionality of the chip as per the specifications. To synthesize the chip, Design Compiler of Foundation Series is used which converts VHDL description to a Gate-level implementation in to a given technology. The synthesizer iii converts the VHDL code in to a Bitmap binary file, which is input to implementation tools. Lastly the synthesized design is verified and various synthesis, post and pre synthesis simulation, pin, place and route reports are analyzed to evaluate and verify the performance of the designed chip. iv