SIMULATION AND PERFORMANCE INVESTIGATION OF MULTI -LEVEL INVERTER FED INDUCTION MOTOR

Abstract

The general trend in power electronics has been to switch power semiconductors at increasingly high frequency in order to minimize harmonics and achieve a smooth drive control. Various PWM techniques have been exploited to limits in this direction. However, this invited various problems, like the increase of switching frequency increased the switching losses, which becomes significant at high power levels. Since the switching in these inverters is directly from positive DC-link voltage to zero or negative, the dv/dt associated is very high for medium and high voltage applications. This large dv/dt generates common mode voltage within the motor windings which results in drive application problems. The common mode voltage enables the motor shaft voltage to build up through electrostatic coupling between the rotor and the 7 frame, resulting in excessive bearing currents, and hence premature bearing failures. High dv/dt also induces corona discharge between winding layers and current flow via the electrostatic coupling formed by stator winding and the grounded frame. This also causes Electromagnetic Interference emission. Multilevel power converters have gained much attention in recent years due to the proven mitigation of various problems faced in the PWM inverters, as cited above. The advantages gained in the multilevel topology make it a candidate for the next generation industrial drive systems. The so-called "multilevel" starts from three levels. The general structure of the multilevel inverter is such as to synthesize a sinusoidal voltage from several levels of DC voltage, which are typically obtained from series connected capacitors across the -available DC-link. Increasing the number of levels produces a fine staircase waveform approaching close to a sinusoidal wave with minimum harmonic distortion. Since the devices are connected in series, low voltage rating devices can be connected to obtain a high voltage output, increasing the voltage and power level handled by the drive. The switching takes place close to output cycle iii frequency, reducing the switching losses. The dv/dt associated is low as the switching takes place between adjacent DC levels. The primary disadvantage of these systems is the large number of switching devices involved. For large number of levels, the system becomes complex due to circuit layout and voltage clamping requirements and hence impractical. Voltage unbalance between various DC levels is yet another problem faced . in this area. This dissertation discusses the operation and performance of various multilevel inverters. The diode-clamp topology for five-level inverter has been selected and simulation and experimental studies have been carried out. The work mainly focuses on the improvement in the voltage THD gained by increasing the levels in the output waveform including the distribution of various harmonics in the harmonic spectrum, the effect of varying frequency on the current THD, design and device count. A modular design in the practical implementation has been chosen, which has various advantages. iv