Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/6592
Full metadata record
DC FieldValueLanguage
dc.contributor.authorAgarwal, Rashmi-
dc.date.accessioned2014-11-03T09:50:54Z-
dc.date.available2014-11-03T09:50:54Z-
dc.date.issued2011-
dc.identifierM.Techen_US
dc.identifier.urihttp://hdl.handle.net/123456789/6592-
dc.guideSaxena, A. K.-
dc.guideManhas, S. K.-
dc.description.abstractIn this research work the behavior of the autonomous oscillator under the influence of an external signal oscillator has been treated. Oscillator can be coupled to each other either bilaterally or unilaterally. Injection locking is the phenomenon in which a periodic signal is injected into an autonomous oscillator results in frequency and phase locking. Frequency-domain and Time-domain delay based model are defined to describe the injection locking in single-ended CMOS inverter based ring oscillator. Oscillators are widely used in wireless communication for clock generation. Injection locking phenomenon can also be used in many applications such as Frequency Synthesis (division and multiplication), multiphase generation or phase noise improvement [2]. In both applications phase noise in the oscillators has great importance. In this work physics of the phase noise in oscillators has been studied to define the parameters on which it depends. Phase noise reduction in mutually coupled oscillatory system has been explored for bilaterally coupled network of two or more oscillators. Phase noise filtering in injection locking is also being exploited. Injection-locked oscillator works by synchronizing the oscillator by the signal which is super-harmonic of the oscillator signal. Two different architectures for ILFD and their noise dynamics have been studied. These architectures are then compared to the conventional dividers for power improvement. This method gives reduction of 69% to 33% in total power consumption for division when compared to TSPC across the Process corners and across the tuning range of 121%. The circuit achieves a phase noise performance of -91 dBc/Hz@ l mHz offset and takes an area of j ust 43 μm2.en_US
dc.language.isoenen_US
dc.subjectELECTRONICS AND COMPUTER ENGINEERINGen_US
dc.subjectFREQUENCY DIVIDERen_US
dc.subjectCOUPLED OSCILLATORen_US
dc.subjectPHASE NOISE REDUCTIONen_US
dc.titleDESIGN OF FREQUENCY DIVIDER USING COUPLED OSCILLATOR AND STUDY OF PHASE NOISE REDUCTIONen_US
dc.typeM.Tech Dessertationen_US
dc.accession.numberG21388en_US
Appears in Collections:MASTERS' THESES (E & C)

Files in This Item:
File Description SizeFormat 
ECED G21388.pdf3.35 MBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.