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DC Field | Value | Language |
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dc.contributor.author | Agarwal, Rashmi | - |
dc.date.accessioned | 2014-11-03T09:50:54Z | - |
dc.date.available | 2014-11-03T09:50:54Z | - |
dc.date.issued | 2011 | - |
dc.identifier | M.Tech | en_US |
dc.identifier.uri | http://hdl.handle.net/123456789/6592 | - |
dc.guide | Saxena, A. K. | - |
dc.guide | Manhas, S. K. | - |
dc.description.abstract | In this research work the behavior of the autonomous oscillator under the influence of an external signal oscillator has been treated. Oscillator can be coupled to each other either bilaterally or unilaterally. Injection locking is the phenomenon in which a periodic signal is injected into an autonomous oscillator results in frequency and phase locking. Frequency-domain and Time-domain delay based model are defined to describe the injection locking in single-ended CMOS inverter based ring oscillator. Oscillators are widely used in wireless communication for clock generation. Injection locking phenomenon can also be used in many applications such as Frequency Synthesis (division and multiplication), multiphase generation or phase noise improvement [2]. In both applications phase noise in the oscillators has great importance. In this work physics of the phase noise in oscillators has been studied to define the parameters on which it depends. Phase noise reduction in mutually coupled oscillatory system has been explored for bilaterally coupled network of two or more oscillators. Phase noise filtering in injection locking is also being exploited. Injection-locked oscillator works by synchronizing the oscillator by the signal which is super-harmonic of the oscillator signal. Two different architectures for ILFD and their noise dynamics have been studied. These architectures are then compared to the conventional dividers for power improvement. This method gives reduction of 69% to 33% in total power consumption for division when compared to TSPC across the Process corners and across the tuning range of 121%. The circuit achieves a phase noise performance of -91 dBc/Hz@ l mHz offset and takes an area of j ust 43 μm2. | en_US |
dc.language.iso | en | en_US |
dc.subject | ELECTRONICS AND COMPUTER ENGINEERING | en_US |
dc.subject | FREQUENCY DIVIDER | en_US |
dc.subject | COUPLED OSCILLATOR | en_US |
dc.subject | PHASE NOISE REDUCTION | en_US |
dc.title | DESIGN OF FREQUENCY DIVIDER USING COUPLED OSCILLATOR AND STUDY OF PHASE NOISE REDUCTION | en_US |
dc.type | M.Tech Dessertation | en_US |
dc.accession.number | G21388 | en_US |
Appears in Collections: | MASTERS' THESES (E & C) |
Files in This Item:
File | Description | Size | Format | |
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ECED G21388.pdf | 3.35 MB | Adobe PDF | View/Open |
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