Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/6179
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dc.contributor.authorUddhavrao, Gajjewar Umakant-
dc.date.accessioned2014-10-12T08:29:31Z-
dc.date.available2014-10-12T08:29:31Z-
dc.date.issued1996-
dc.identifierM.Techen_US
dc.identifier.urihttp://hdl.handle.net/123456789/6179-
dc.guideAgarwal, R. P.-
dc.description.abstractA Fault Simution Tool has been developed which simulates circuit description and gives fault coverage of the applied test vectors. The user has to give circuit description using circuit description language, the compiler for which has been written using lex and yacc UNIX tools. The fault simulator uses stuck --at - fault model for circuit to be simulated. It uses Parallel Pattern Single Fault Propagation (PPSFP) algorithm for evaluating fault coverage of test vectors. The PPSFP algorithm is faster than other algorithms since it uses combination of Parallel Pattern Evaluation and Single Fault Propagation techniquesen_US
dc.language.isoenen_US
dc.subjectELECTRONICS AND COMPUTER ENGINEERINGen_US
dc.subjectFAULT SIMULATIONen_US
dc.subjectSIMULATION TOOLen_US
dc.subjectVLSI CIRCUITSen_US
dc.titleFAULT SIMULATION TOOL FOR VLSI CIRCUITSen_US
dc.typeM.Tech Dessertationen_US
dc.accession.number247066en_US
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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