FAULT SIMULATION TOOL FOR VLSI CIRCUITS

Abstract

A Fault Simution Tool has been developed which simulates circuit description and gives fault coverage of the applied test vectors. The user has to give circuit description using circuit description language, the compiler for which has been written using lex and yacc UNIX tools. The fault simulator uses stuck --at - fault model for circuit to be simulated. It uses Parallel Pattern Single Fault Propagation (PPSFP) algorithm for evaluating fault coverage of test vectors. The PPSFP algorithm is faster than other algorithms since it uses combination of Parallel Pattern Evaluation and Single Fault Propagation techniques