Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/6179
Title: FAULT SIMULATION TOOL FOR VLSI CIRCUITS
Authors: Uddhavrao, Gajjewar Umakant
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;FAULT SIMULATION;SIMULATION TOOL;VLSI CIRCUITS
Issue Date: 1996
Abstract: A Fault Simution Tool has been developed which simulates circuit description and gives fault coverage of the applied test vectors. The user has to give circuit description using circuit description language, the compiler for which has been written using lex and yacc UNIX tools. The fault simulator uses stuck --at - fault model for circuit to be simulated. It uses Parallel Pattern Single Fault Propagation (PPSFP) algorithm for evaluating fault coverage of test vectors. The PPSFP algorithm is faster than other algorithms since it uses combination of Parallel Pattern Evaluation and Single Fault Propagation techniques
URI: http://hdl.handle.net/123456789/6179
Other Identifiers: M.Tech
Research Supervisor/ Guide: Agarwal, R. P.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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