TIMING MODEL FOR SEQUENTIAL CIRCUITS

Abstract

Characterizing setup/hold times of latches and registers, a vital part for achieving timing closure of large digital designs, it takes large computational time. Accurate estimation of setup/hold time in Static Timing Analysis (STA) using Look Up Table (LUT) is a major challenge in Nano-meter range VLSI circuits. Issues with LUT are mostly due to the arbitrary choice of input signal transition time (TR) and load capac-itance (CL ) and the large number of simulations to be performed for characterizing an entire standard cell library. In this dissertation, we present setup time models for true single phase clocked (TSPC) [1], clocked CMOS (C2MOS) [2] and static latches [3]. We use these models to speed up standard cell library characterization. We model the setup time linearly with input transition time TR and load capacitance CL. We also express the region of validity of model as a function of TR and CL. We also derive the relationship of the model coefficients with size of the CMOS latch standard cell, temperature of operation, supply voltage and threshold voltage Vh: We use these relationships to simplify latch setup time characterization methodology, eliminating the necessity of about 70% simulations. We show that our model and method of improving characterization process are valid with technology scaling. zv