IMPLEMENTATION OF DIGITAL SIGNAL PROCESSING ALGORITHMS ON FPGA

Abstract

Signal processing building blocks are required to perform efficient and fast in real-time computing environment to meet the multimedia application-computing requirement. Though DSP Processors are available these processors execute the different blocks on a fixed hardware like Multiplier Accumulator (MAC), this requires fetching and decoding of instructions that increases the execution delay. To meet high performance computing, it is a general practice to use Application Specific Integrated Circuits (ASICs) and / or Application Specific Instruction Set Processors (ASIPs). In ASICs consist of fixed hardware, which one cannot change after fabrication. ASIPs will increase instruction fetching decoding delay though it provides flexibility. To fulfill the gap between ASIC and ASIP reconfigurable computing has been introduced. In reconfigurable computing environment one can have performance like ASIC while having the flexibility of general-purpose processor. The objective of this thesis is design, modeling, simulation and synthesis of basic DSP Building blocks such as FFT, FIR and IIR filters. The various sub-blocks for these algorithms namely the multiplier, adder, subtractor and MAC are designed. Initially the Algorithms are studied and the problem statement is formed, and then this is coded using a suitable Hardware Descriptive Language (HDL) and further, it is synthesized on an appropriate Field Programmable Gate Array (FPGA) kit which supports the various Digital Signal Processing Algorithms. VHDL and Verilog, both are hardware descriptive languages that are generally used. Here in this thesis, the algorithms are implemented using the VHDL coding. The various orders and types of FIR filters, IIR filters are implemented. The various algorithms implemented are validated by carrying out and comparing the pre-synthesis and post-synthesis results. A new method for validation called Hardware-Software Co-simulation is also implemented.