SHORT CIRCUIT STUDY OF LARGE POWER SYSTEM

Abstract

The work presented in this dissertation deals with short circuit study of Large Power System. As the size of the power system increases it becomes increasingly difficult to accommodate the problem within the core memory of the computer. Sparsity techniques has been used in the formation of bus admittance matrices, their LDU decomposition and fast forward and backward substitution solution to reduce core memory requirements and execution time. In the process the formation of the complete bus impedance matrix is avoided and only relevant column of terms of the bus impedance matrix for short circuit calculation are computed. Computer programs have been developed based on the foregoing concept for bus short circuit calculation and calculation of line fault currents. The programs developed havebeen tested on 'TATA ELXSI POWER SERIES - 3220' computer with test data.