STUDY OF PARASITIC EFFECTS IN FINFETS

Abstract

As the level of integration is increasing in the field of IC's, it is very important to scale down the device dimensions also. But beyond a certain extent device/circuit performance starts degrading due to short channel effects. FinFETs are most promising substitutes for replacing bulk CMOS in nano scale circuits due to their excellent `Short channel effects' immunity. .FinFET circuits are facing some issues over CMOS circuits, like width quantization and higher parasitics. These need special attention to evaluate circuit prospects of FinFETs.The device characteristics and fabrication aspects of FinFETs have got considerable attention in the last half decade. FinFET devices with source drain underlaps are particularly attractive due to their high Ion/Ioff ratios. Researchers have proposed several FinFET circuit architectures, which are mostly based on the flexibility offered by the device but efficient circuit designing using FinFETs is still a major challenge. To design circuits at scaled nodes, there is a need for technology aware circuit design methodology that considers device architecture and technology challenges to achieve optimal design. We show in our work that a thorough understanding of the device parasitics is crucial in improving FinFET circuit performance. We report a new phenomenon of a strong dependence of effective values of FinFET gate and parasitic capacitances on transition time of its terminal voltages. We explain this phenomenon by observing that the drain extension region forms a transistor which shields gate fringing field capacitances. Analysis of parasitic effects in a FinFET inverter has been carried out. Different variations of parasitic capacitance of a FinFET inverter with circuit parameters like load capacitance and input transition time , are qualitatively analyzed by using three transistor equivalent circuit of a iv FinFET device. In the next section this analysis is done for different device configurations like different extension lengths of FinFET, different doping profiles. In the next section a circuit of two cascaded inverters is made and the same phenomenon is analyzed for this circuit for various sizes of driver inverter and load inverter. We show that an understanding of this phenomenon is essential for underlap FinFET circuit design. Next we have shown simulation results and extracted data to support our qualitative study. Impacts of these variations on the circuit performance have also been analyzed. We have shown through results that these parasitic variations have adverse effects on the circuit performance and need to be modeled properly in order to have an efficient circuit design methodology using FinFETs