Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/4051
Full metadata record
DC FieldValueLanguage
dc.contributor.authorMittal, Shailesh-
dc.date.accessioned2014-10-05T09:45:40Z-
dc.date.available2014-10-05T09:45:40Z-
dc.date.issued2012-
dc.identifierM.Techen_US
dc.identifier.urihttp://hdl.handle.net/123456789/4051-
dc.guideYadav, K. L.-
dc.guideKaushik, B. K.-
dc.description.abstractDevice scaling in deep Submicron technology shrinkage the spacing between adjacent interconnect, which leads to increase coupling effect between wires. Continuous device scaling much improved the gates delay. However, interconnect delays have not scaled in that proportion Therefore a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects becomes necessary. This thesis presents the description of a finite difference time domain (FDTD) method that is intended for estimation of voltages and currents on transmission line. Interconnect performance such as crosstalk, delay, crosstalk induce delay are analyzed using FDTD technique. For motivation, analytical results based on proposed model is also compared with HSPICE simulated result. Analytical results are observed in closed agreement with HSPICE results, which proves the validity of proposed model.en_US
dc.language.isoenen_US
dc.subjectPHYSICSen_US
dc.subjectFDTD TECHNIQUEen_US
dc.subjectHSPICEen_US
dc.subjectINTERCONNECT PERFORMANCEen_US
dc.titleANALYSIS OF INTERCONNECT PERFORMANCE USING FDTD TECHNIQUEen_US
dc.typeM.Tech Dessertationen_US
dc.accession.numberG21893en_US
Appears in Collections:MASTERS' THESES (Physics)

Files in This Item:
File Description SizeFormat 
PHDG21893.pdf3.1 MBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.