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|Title:||LEAKAGE CURRENTS' REDUCTION IN SUB-MICRON DIGITAL CMOS CIRCUITS|
|Authors:||Lalwani, Mukesh Kumar|
|Abstract:||In each generation of VLSI Technology, with the help of aggressive scaling of semiconductor devices, rapid increase in the number of CMOS transistors on chip has been achieved. Now to control the resulting switching power (dynamic power), successive technology generations have relied on reducing the supply voltage. In order to maintain performance at the reduced supply voltage has required a corresponding reduction in the transistor oxide thickness and also in the threshold voltage of the transistor. As a result of this reduction in the transistor oxide thickness. and in the threshold voltage, the CMOS transistors dissipate standby leakage power (static power). Thus, the performance improvement in the IC's through device scaling has been accompanied by an increase in the static power dissipation. Since last few years in the way VLSI field, the capacity of on-chip memory is rapidly increasing to improve overall performance. According to the ITRS roadmap in 2001, memory will occupy about 90% of chip area by 2013. In such a memory-rich chip, the leakage current of a SRAM dominates the standby current. Thus, the reduction of the standby leakage current of SRAMs is the most important factor to achieve low power consumption. Since gate leakage current is expected to be the dominant leakage component for future CMOS devices, circuit level techniques need to be reinvestigated for gate leakage reduction. High leakage current in deep-sub micrometer regimes is also becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This thesis work reviews various transistor intrinsic leakage mechanisms, introduced in past one decade. Finally, the work explores different circuit level techniques to reduce the leakage currents of SRAM and combinational circuits. In this work, two approaches for reducing gate leakage currents were examined in detail. In one approach, the supply voltage was reduced, while in the other approach, the potential of the ground node was raised. In both the approaches the effective voltage across cell was reduced during inactive mode using a dynamic self-controllable switch. It is proposed that the scheme in which supply voltage level is reduced is more efficient in reducing gate leakage than the one in which ground node potential is raised.|
|Research Supervisor/ Guide:||Nath, R.|
Tondon, V. K.
|Appears in Collections:||MASTERS' THESES (Physics)|
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